[chbot] Any Xilinx Vivado experts out there?

[Charles Manning]

Botters,

I have a very frustrating thing I am trying to solve with using Xilinx
Vivado to set up what should be a very simple bitstream.

I am using a Zynq and all I want to do is hook up the EMIO RTS and CTS
signals to PL pins.

I have taken an existing "getting started" Zynq design for the Zynq and
have turned on the extra UART signals so I can see them in the processor
block diagram in block design view.

Now I'm struggling with what should be the easy bit: define input and
output pins and hook them up.

I tried "make external" which creates ports for these signals, but those do
not turn up in the pin planner.

Can anyone lead me through this?

Thanks

Charles
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