[chbot] New chocolate fish challenge

[hamster]

The real reason is that I have a spare small FPGA board that I don't
have a use for, and I find building logic in an FPGA is easier than
building S/W when I want to be sure that I get good timing and a good
display. 

Also, I was initially thinking of using individual I/O pins
for controlling the segment drivers, but soon gave that away to a
daughter-boards with shift register and discrete constant current
drivers on it. 

 With all the segments driven the display will require
1.2A @ 15V, with maybe 5W being lost as heat on the driver PCBs, so they
couldn't be too small. 

If anybody wants to bling their Xmas tree with
custom LEDs I'll soon have some extras PCBs and parts available for the
cost of a coffee, if you feel like a bit of soldering up a bit of Xmas
joy.... 

Mike 

On 20.11.2014 13:18, Charles Manning wrote: 

> Well an
FPGA itself is overkill, but a clock built from logic gates uses a lot
less resources than one built with a CPU.
> 
> The "counter tricks"
shown here reduce the number of gates required as well as the number of
bit transitions. That saves money and energy.

 
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