[chbot] New chocolate fish challenge

[Charles Manning]

Well an FPGA itself is overkill, but a clock built from logic gates uses a
lot less resources than one built with a CPU.

The "counter tricks" shown here reduce the number of gates required as well
as the number of bit transitions. That saves money and energy.



On Thu, Nov 20, 2014 at 12:47 PM, Volker Kuhlmann <list0570 at paradise.net.nz>
wrote:

> On Thu 20 Nov 2014 09:12:33 NZDT +1300, Michael Field wrote:
>
> > that hard as knowing that a 5-bit two-tap design is possible the are
> > only 4 options (0x30, 0x28, 0x24, 0x22 and 0x21).
>
> I thought the taps can be anywhere, wouldn't that make it 10
> possibilities? However still small enough for a bit of
> lets-see-what-happens.
>
> And you're building your clock with an FPGA? Not because you need to, or
> because it would be sensible, or because it would be cheap, but just
> because you can? Sounds like fun.
>
> Volker
>
> --
> Volker Kuhlmann
> http://volker.top.geek.nz/      Please do not CC list postings to me.
>
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