[chbot] RISC-V stuff.

[Charles Manning]

Perhaps 2 meetings...

General interest meeting + a high brow meeting.



On Thu, Mar 7, 2019 at 1:06 PM Mark Atherton <markaren1 at xtra.co.nz> wrote:

> Mike,
>
> Any chance Bruce Holt might be available on 18th March to attend our
> meeting -- sounds like an ideal speaker.
>
> -Mark
>
> On 7/03/2019 10:10 AM, Charles Manning wrote:
>
> Hamster. Yes please v interested.
>
> I'm looking at using a RISCV core in an FPGA.
>
>
>
> On Thu, Mar 7, 2019 at 10:02 AM hamster <hamster at snap.net.nz> wrote:
>
>> Hi,
>>
>> Yesterday I received a Sipeed MAiX M1w arrive in the mail from Seeed
>> Studio. https://www.seeedstudio.com/sipeed
>>
>> It is RISC-V 64-bit dual core 400MHz CPU, 8MB of RAM, LCD and Camera
>> interfaces, WiFi, and lots of odd hardware features "AI accelerator", "FFT
>> accelerator"...
>>
>> A few lines of microPython later the camera and LCD were up and running.
>> Not bad for < $US20.
>>
>> I posted on Twitter about it, and Bruce Holt (ex Samsung R&D, moving to
>> the US to be with SiFive, knows a ton about a lot of CPUs) said that he
>> would be in town sometime soon and would be happy to meet up and chat.
>>
>> Anybody else interested?
>>
>> Time and place TBA.
>>
>> Mike
>>
>
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