[chbot] SDR stuff - "Field programmable RF"

[Charles Manning]

On Saturday 20 April 2013 13:14:20 Mark Atherton wrote:

> support this part. Takes 180 sec to compile a 5k
> LE design here, so the idea of trying 115k... anyone got a spare Cray ?
>
C'mon Mark, stop whinging.

You're old enough to remember the, ahem, Good Old Days!

In 1996/7, I upgraded my already new Pentium to be able to build for Xilinx 
FPGAs.

First I splashed out and bought a whopping 1.2 Gbyte disk drive which all my 
colleagues drooled over.

I then bought more RAM (32MB, maybe it was only 16MB...)

And I was so chuffed that a 3k gate design built overnight!