[chbot] video test card, ISS test generator project etc.

Mark Atherton markaren1 at xtra.co.nz
Mon Mar 18 18:44:13 GMT 2013

Hi All,

Last night there was talk about the generation of an electronic test 
pattern, latest is here www.idesignz.org/DATV_test_card/ariss.ts

The file started life as 360 GIF images 720 x 480 (NTSC broadcast 
dimensions) that were encoded to MPG program stream (normal desktop 
MPG), then re-multiplexed to Transport Stream, with the addition of 
some System Information tables.

The base GIF was created using ImageMagick, using a mass of hand 
created vectors, clock was then added added. Clock automation was 
created by some C which draws radial lines, to form the second hand - 
actually the C creates a script that ImageMagick uses to create the 
final rendered frames.

The file is an MPG Transport Stream, you may need to load an 
appropriate video decoder since this isn't currently a main-stream 
video format. If anyone is interest in tinkering, the project is open 
source, so will be happy to pass on scripts etc, that are required 
for it's creation.


Somebody later also asked about the origins of the project. Briefly 
it is an extension of DigiliteZL, 
http://www.idesignz.org/DigiLiteZL/DigiLiteZL.htm which was developed 
as an FPGA based education tool so real-time video could be 
experimented with. This needed to be converted into a stand-alone 
unit so it can be used for ground-station alignment as part of the 
Digital-TV-from-space project being managed from the International 
Space Station, by NASA.

The USB input source has been replaced with a (very) high speed SD 
card interface where the Transport Stream file is loaded. A 32 bit 
softcore processor (NIOS II) then manages the user interface, which 
may be controlled via command line (9600 baud) or by DIP switches 
(for stand-alone operation). The UI is written in C.

In stand-alone mode, the test file is loaded into SDRAM using the 
CPU, using an Altera IP core, and a home-cooked stripped down FAT16B 
core.Loading occurs at about 500k bytes per sec. The file copy in 
SDRAM is then copied at video rate into the FIFO bridge which feeds 
the modulator. The PLL on board the FPGA has been updated to support 
a couple of symbol rates.

In the long term, all manner of opportunities exist given that data 
can now be fetched off the SD card in real time, and the interface to 
the modulator is now understood. Just finished testing the release 
candidate for the system, now need to move onto completing 
documentation to support the guys making some of these units in the US.

Current bottleneck is using the CPU to copy video from memory to 
modulator in C. Should be possible to speed this up by re-doing it in 
assembler. Also going to investigate using an Avalon-Master DAM 
controller. May need to re-do the baseband I/Q filters, and it may 
actually be easier to do this filtering at video rate using the 80% 
odd spare silicon available in the FPGA there are about 300-odd 
multipliers left, so a couple of video FIR filters may just fit.

Anyway, yet another adventure...



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