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How are you testing that the first DMA is complete before you start overwriting the buffer with the next payload?<br>
<br>
/Bevin</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Chchrobotics <chchrobotics-bounces@lists.ourshack.com> on behalf of chchrobotics-request@lists.ourshack.com <chchrobotics-request@lists.ourshack.com><br>
<b>Sent:</b> Wednesday, February 9, 2022 1:00 AM<br>
<b>To:</b> chchrobotics@lists.ourshack.com <chchrobotics@lists.ourshack.com><br>
<b>Subject:</b> Chchrobotics Digest, Vol 173, Issue 8</font>
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Today's Topics:<br>
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1. Re: Volatile struct puzzle (Robin Gilks)<br>
<br>
<br>
----------------------------------------------------------------------<br>
<br>
Message: 1<br>
Date: Tue, 8 Feb 2022 13:48:38 +1300<br>
From: Robin Gilks <gb7ipd@gmail.com><br>
To: Christchurch Robotics <chchrobotics@lists.ourshack.com><br>
Subject: Re: [chbot] Volatile struct puzzle<br>
Message-ID:<br>
<CAPfE9Ugb37NE-6DqjbL8b0U-na52HO4WMHYBtXNaRidwMUW04g@mail.gmail.com><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
I think I understand what SHOULD work, but it doesn't!!<br>
<br>
JPEG encode occurs in 3 (4) stages<br>
<br>
1. prepare first block bitmap data by converting to YCbCr. Do a<br>
SCB_CleanDCache_by_Addr() cache flush to make sure it's all in RAM and not<br>
cache and accessible to DMA<br>
2. after processing, flush the cache with SCB_InvalidateDCache_by_Addr()<br>
to ensure the data read not stale before writing to filesystem<br>
3. prepare the next YCbCrblock and like (1) flush the cache to make sure<br>
its all accessible to DMA<br>
4. repeat 2-3 until all bitmap data done<br>
<br>
Now I'm really stuck (other than random rearrangements of the code)<br>
<br>
<br>
On Tue, Feb 8, 2022 at 1:38 PM Robin Gilks <gb7ipd@gmail.com> wrote:<br>
<br>
> I think I understand what SHOULD work, but it doesn't!!<br>
><br>
> JPEG encode occurs in 3 (4) stages<br>
><br>
> 1. prepare first block bitmap data by converting to YCbCr. Do a<br>
> SCB_CleanDCache_by_Addr() cache flush to make sure it's all in RAM and not<br>
> cache and accessible to DMA<br>
> 2. after processing, flush the cache with<br>
> SCB_InvalidateDCache_by_Addr() to ensure the data read not stale before<br>
> writing to filesystem<br>
> 3. prepare the next YCbCrblock and like (1) flush the cache to make<br>
> sure its all accessible to DMA<br>
> 4. repeat 2-3 until all bitmap data done<br>
><br>
> Now I'm really stuck (other than random rearrangements of the code)<br>
><br>
><br>
> On Mon, Feb 7, 2022 at 3:01 PM Charles Manning <cdhmanning@gmail.com><br>
> wrote:<br>
><br>
>> Hi Robin<br>
>><br>
>> The packing of the structure should not be a factor unless you are<br>
>> fiddling with the packed attribute.<br>
>><br>
>> When we're talking about caching then there are many things that enter<br>
>> the picture.<br>
>><br>
>> You say that the buffer itself (which I expect is the target of the DMA<br>
>> rather than anything else) has the correct caching attributes. What are<br>
>> those? From a brief glimpse at the Cortex M7 manuals, you should be<br>
>> ensuring this has the shared attribute. If this is set correctly then the<br>
>> caching should not matter. What have you done to check the caching is<br>
>> correct?<br>
>> Do not assume that the caching is correct from compiler attributes. Those<br>
>> might not match the settings in the MMU.<br>
>><br>
>> What you are observing is that in one case the cache appears to be<br>
>> fetched correctly and in the other not.<br>
>> This can be caused by execution of code far away from this point due to<br>
>> how the cache works.<br>
>><br>
>> A compiler change can reorder instructions and data accesses(especially<br>
>> at -O3). THis can completely change the CPU's interaction with the cache.<br>
>> Throw in an out of order CPU like the M7 and a lot can change.<br>
>><br>
>> A cache has multiple cache lines and the address being accessed can only<br>
>> map to a few of these cache lines (termed a set). If other code elsewhere<br>
>> needs something in the cache that maps to the same set, then this could be<br>
>> forcing a new cache read - causing the data to be healthy. If, however, the<br>
>> cache is not being refreshed, then the old cached value might be used<br>
>> forever.<br>
>><br>
>> Assuming the DMA controller is only modifying the buffer, I would try<br>
>> adding the following just before accessing the buffer:<br>
>><br>
>> /* Force fresh data into the cache */<br>
>> uint32_t jpeg_base = ((uint32_t) JPEG_Data_Buffer) & (~0x1f); /* Calc<br>
>> base 32-byte boundary */<br>
>> uint32_t n_bytes = ((uint32_t) JPEG_Data_Buffer) - jpeg_base +<br>
>> sizeof(JPEG_Data_Buffer);<br>
>> SCB_InvalidateDCache_by_Addr(jpeg_base, n_bytes);<br>
>> ... now access stuff in the cache.<br>
>><br>
>><br>
>><br>
>><br>
>><br>
>><br>
>><br>
>><br>
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