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<p class="MsoNormal"><span style="mso-fareast-language:EN-US">Hi Charles / All,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US">From what I have seen and my minimal go at the Intel HLS tool - Intel and Xilinx HLS tools rely on a deep understanding of your hardware to be close to efficient – manufacturer claims of 10-15% premium
to hand crafted – they are a great prototyping tool and it’s too easy to push go and get 100KLE design out for something that can be hand coded to 5KLE … that being said, some thought and reading the manuals will yield quite a good/reasonable/workable result
most times.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US">OpenCL is another SW -> HW mapping, but is very much a software centric flow with the FPGA obfuscated but it needs a CPU to schedule the dataflow and kernels.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US">Regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US">Steve.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span lang="EN-US">From:</span></b><span lang="EN-US"> Chchrobotics <chchrobotics-bounces@lists.ourshack.com>
<b>On Behalf Of </b>Charles Manning<br>
<b>Sent:</b> Friday, 10 August 2018 9:13 AM<br>
<b>To:</b> Christchurch Robotics <chchrobotics@lists.ourshack.com><br>
<b>Subject:</b> [chbot] Xiilinx HLS any good?<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hello All<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Has anyone done any real work, or know of any real work, that has been done with the Xilinx HLS tools.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">This is the toolset that takes code written in C/C++ and munches it down to run on an FPGA.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">There is obvious appeal from a 50,000 ft perspective that you can write a program in C, tweak it a bit and re-compile it and voilà, you're an FPGA programmer!<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">The sceptic in me says that nothing comes for free. You must be giving something away. C lacks the expressiveness for some CPU operations. It surely lacks the ability to convey concepts that Verilog and VHDL do.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">This suggests to me that an FPGA executing HLS is inherently going to need more resources (read bigger, more expensive FPGAs) and need more power (ie. bigger battery, heatsinks,...) than the same function implemented in Verilog.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Has anyone experience to either refute my assertions or back them up?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Charles<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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